Tsinghua University · COMPUTER-ORGANIZATION

Computer Organization

计算机组成原理

Tsinghua's 2025 computer-organization course using RISC-V and THINPAD to study instruction sets, data representation, arithmetic hardware, CPU datapaths and control, pipelines, caches, virtual memory, buses, interrupts, and I/O through written work and processor labs.

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Official unit 1: Computer-System Introduction

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Subject：Computer Systems

Level：Undergraduate

Suggested stage：Years 2–3 (inferred)

Public-material edition：2025

Language：Chinese

Videos：Not verified

Assignments / solutions：Available / Not verified

Prerequisites

Digital logicC programming

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All official course content

Lectures, video, assignments and exams are separated so you do not have to hunt through the course homepage.

32 direct tasks

▶Lectures, video & readingCourse content in the official sequence22

Official unit 1: Computer-System Introduction Official unit 2: RISC-V and THINPAD Instructions Official unit 3: Data Representation and Error Control Official unit 4: Arithmetic and Hardware Implementation Official unit 5: Instruction-Set Design Official unit 6: RISC-V Instruction Set Official unit 7: Datapaths Official unit 8: Single-Cycle Processors Official unit 9: Multi-Cycle Processors Official unit 10: Pipelined Processors Official unit 11: Structural and Data Hazards Official unit 12: Control Hazards Official unit 13: RISC-V Interrupts and Exceptions Official unit 14: Memory Hierarchy and DRAM Official unit 15: SRAM and Processor Caches Official unit 16: Cache Design Official unit 17: Virtual Memory Official unit 18: External Storage Official unit 19: I/O Methods Official unit 20: Buses Official unit 21: Interfaces and External Devices Official unit 22: Processor-Architecture Frontiers

✓Assignments & practiceOpen the matching problem or assignment page4

Official written assignment 1 Official written assignment 2 Official written assignment 3 Official written assignment 4

◆Labs & projectsCourse projects, labs and milestones6

Official laboratory 1: Assembly and Monitor Program Official laboratory 2: ALU and Register File Official laboratory 3: SRAM Controller Official laboratory 4: Memory and Serial-Port Bus Official laboratory 5: Processor Implementation Official laboratory 6: Five-Stage Pipelined RISC-V Processor

Official resource hubs

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Official 2025 lecture, homework, and laboratory scheduleTsinghua University Computer Laboratory Teaching Center ↗

Official processor laboratory guideTsinghua University Computer Laboratory Teaching Center ↗

Official RISC-V emulator and laboratory environmentTsinghua University Computer Laboratory Teaching Center ↗

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Every link points to an official university or course-team page. The year identifies the linked public-material edition, not necessarily the latest on-campus offering; a school may have newer materials that are not public. Unknown facts remain unverified rather than guessed.

Tsinghua University Computer Laboratory Teaching Center · verified 2026-08-22

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